(1) Field of the Invention
The invention relates to the field of semiconductor manufacturing, and more particularly to a novel method of forming an isolation area on a semiconductor device.
(2) Description of the Prior Art
For MOS circuits, threshold voltage for the field-oxide areas must be higher to isolate individual devices. Many isolation methods have been proposed such as Localized Oxidation Isolation (LOCOS), polybuffered LOCOS (PBLOCOS) and Shallow Trench Isolation (STI). The present invention relates to the process of shallow trench isolation. In shallow trench isolation, trenches about 0.3 to 0.8 um. deep are anisotropically etched into the silicon substrate through dry etching. Active regions are those that are protected from the etch when the trenches are created. Next, a CVD oxide is deposited on the wafer surface and then etched back so that it remains only in recesses, with its top surface at the same level as the original silicon surface. Etchback is performed using a sacrificial photoresist method. This technique has the advantage of having no birdbeak (a problem experienced with the LOCOS technology) and no encroachment. Also, when two devices are separated by a trench, the electrical field lines have to travel a longer distance and change direction twice, so they are considerably weakened. Therefore, trenches in sub-micrometer dimensions are adequate for isolation to prevent punch-through and latch-up phenomena. Shallow-trench techniques however are complicated while in the past LOCOS and Poly-Bufferred LOCOS (PBLOCOS) have provided satisfactory results. Shallow-trench techniques are therefore only slowly being used extensively in the industry.
The oxide lost at the shoulders of a shallow trench can induce junction leakage and Kirk's effect of the devices. This latter effect can be explained as follows. As the collector-current density in an npn transistor increases, the density of electrons transported across the C-B junction also increases. When this density of electrons crossing the C-B junction becomes comparable to the doping on the collector side of the space-charge region, the total charge in this region becomes significantly reduced from that under low-level injection conditions, leading to a lower electric-field gradient in the C-B junction. Since the collector voltage is constant, the integration of the electric field will remain the same, with or without current. However, with a lower maximum electric-field strength, the space-charge region edge in the base moves toward the collector, effectively increasing the base width. This phenomenon is referred to as the base push-out effect or the Kirk effect.
The oxide loss of STI is due to wet etching processes. For wet etching, lateral etching cannot be avoided. If, on the other hand, the loss of oxide can be increased, this excess oxide can be used to form a space layer at the shoulders of the trench that functions as a protection layer. This wider space layer results in a reduction of junction leakage current.
Referring now specifically to FIG. 1, there is shown a Prior Art cross section of the Shallow trench isolation region 10. In shallow trench isolation, trenches 10 are anisotropically etched into the silicon substrate through dry etching. The trench 10 typically has a depth within the range of about 3000 to 4000 Angstrom. Active regions 14 are those that are protected from the etch when the trenches are created. Next, a CVD oxide is deposited on the wafer surface and then etched back so that it remains only in recesses, with its top surface at the same level as the original silicon surface. Etchback is performed using a sacrificial photoresist method.
The cross section of FIG. 1 shows the typical formation of a STI region 10, including the phenomenon of the loss of the shoulders 16 of the STI. This loss of the shoulders 16 results in previously highlighted negative effects in the formation of the STI, further processing steps within the scope of the present invention will prevent the formation of the shoulders 16. The STI region 10 is filled using Field Oxide (FOX).
In the salicidation process, to which the invention also applies, the entire source and drain regions and the top of the poly-silicon gate of a MOSFET are covered with a low resistivity metallic thin film. This is attractive because such a film is formed using a self-aligned process that does not require any additional masking steps.
U.S. Pat. No. 5,134,089 (Barden et al.) shows a process of (1) form Field oxide 14 (2) etch Field oxide, see FIG. 4 (3) grow thermally a second oxide layer over the field oxide, see FIG. 5, col. 3, lines 54-64 (4) dry etch second oxide to form spacer, see FIG. 6. Barden appears to show the same steps as the invention but differs in that Barden grows a FOX (not STI) and grows a 2nd oxide layer (invention uses HDPCVD Oxide).
U.S. Pat. No. 5,731,241 (Jang et al.) teaches a FOX with a self aligned oxide sacrificial layer. However, Jang's sacrificial layer is above the surface and does not form spacers.
U.S. Pat. No. 5,554,540 (Hsue et al.) shows a method for forming a sacrificial layer over a FOX and etching back the sacrificial layer.
U.S. Pat. No. 5,118,641 (Roberts) shows a SiN spacer on a FOX. U.S. Pat. No. 5,410,176 (Liou et al.) teaches a method for forming a SiO.sub.2 spacer with STI. U.S. Pat. No. 5,801,082 (Tseng) shows a STI method using a SIN and SOG overlayers.